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阻容原件的质量是会对音色产生一些影响,但不是问题的主要方面,
主要是晶体管的工作点,JC-2的原作者John Curl 就说过,增加JC-2的Rd不是不可以,而是那样会使转换速率受影响,那样改后就不是JC-2了。
不同参数的JFET有其各自的Rs最佳参数。我仿真也发现,对于在JC-2的输入级的同一种JFET,不同的Rs,其1Hz~200Hz的线性是不同的。
调音如果忘记在主动原件上下功夫过分强调阻容原件的补品什么的恐怕事倍功半。
在diyaudio.com Aneat问:
less than 15mA why is not recommend for?
when Idss is smaller we can increase Rd & decrease Rs,the way whether not good?
6th June 2010, 01:07 PM
John Curl 回答:
Sorry that I did not get back to answer questions, I didn't see this thread for awhile.
Unfortunately, I cannot give additional info on the JC-2 attenuators, as I did not design them.
The original JC-2 design was done in 1973, or 37 years ago. At that time, all we had available to us were Siliconix j-fets, in general, and for special applications, Union Carbide, Motorola, or Crystalonics.
The JC-2 phono input stage used Siliconix J110 input devices that are high current switches, that usually have an Idss of over 20 ma. The input devices were used at about 15 ma ea for lowest possible input noise. When you change the Id of the input devices in order to use lower Idss types, then you MUST change the load resistors, and this LOWERS the open loop bandwidth. Still, the change is not too great, IF you use high Idss devices like the 2SK170 V series. Running at 1/2 the originally designed current is not too different, BUT it will be another design if you run less.
The output j-fets of the phono stage. Lowering the Idss on these devices will lower the slew rate significantly, if taken too far.
The same problem with the complementary j-fets in the input driver stage. It is designed with a very high open loop bandwidth, on purpose, and this will be lost IF the input stage load resistors are increased too much. Still the V series 2SK170 and 2SJ74 series will work pretty well, for the output of the phono stage and the input of the line driver amp, with resistor changes.
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"Condemnation without Examination is Prejudice"
6th June 2010, 06:30 PM
这Lowering the Idss on these devices will lower the slew rate significantly, if taken too far 是从上面的叙述中摘出的一句话,这句话的中译文:如果使用的器件其Idss比原设计少太多将明显减慢转换速率。 |
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